1. Field of the Invention
The present invention relates to a technique of manufacturing a semiconductor device. More particularly, it relates to a semiconductor device including a copper interconnect line, and method of manufacturing the same.
2. Description of the Background Art
In an uppermost interconnect layer of a semiconductor device, a pad (bonding pad) is generally provided to be bonded to a wire which connects a lead of a package for holding the semiconductor device and the uppermost interconnect layer, for example. As an example, gold is a common material for a wire.
Resulting from a growing trend in recent years toward shrinkage and higher integration of a structure of a semiconductor device, and toward speedup of operations thereof, importance of reduction in interconnect resistance has been increasing. In response, instead of aluminum conventionally used, copper has been widely employed as a metal interconnect material.
However, copper has poorer adhesion to gold than aluminum. Resulting from the use of copper to form an interconnect line, a pad may also be formed from copper. In this case, poor adhesion between the resultant pad and a gold wire results in the problem that the wire bonded to the pad is likely to fall off, causing deterioration in reliability of operations of the semiconductor device or reduction in yield.
In response, in a semiconductor device using a copper interconnect line, an aluminum pad area may be provided on a surface of the copper interconnect line, the exemplary structure of which is introduced in Japanese Patent Application Laid-Open No. 2-123740 (1990) (pp. 3-5 and FIGS. 1-3), in Japanese Patent Application Laid-Open No. 11-135506 (1999) (pp. 3-4 and FIGS. 1-4), or in Japanese Patent Application Laid-Open No. 10-340920 (1998) (pp. 3-6 and FIGS. 1-4). In this structure, the pad area to which a wire is to be bonded includes aluminum. Therefore, while allowing reduction in interconnect resistance by the use of copper therefor, good adhesion between the pad area and the wire is obtained.
In the semiconductor device disclosed in Japanese Patent Application Laid-Open Nos. 2-123740 (1990), 11-135506 (1999) or 10-340920 (1998), an aluminum pad area is provided on a surface of a copper interconnect line. Therefore, in a structure including the pad area and the copper interconnect line, mechanical strength may be weakened.
A method of manufacturing a semiconductor device having a copper interconnect line generally employs a damascene process. For example, a copper interconnect line is formed by the damascene process, and thereafter, an aluminum pad area is provided thereon, as disclosed in Japanese Patent Application Laid-Open Nos. 11-135506 (1999) and 10-340920 (1998). This method requires respective steps to form the interconnect line and the pad area, causing complication of manufacturing steps and increase in number thereof.
In a wire bonding step generally employed, pressing a wire against a pad area on a semiconductor device with a tip of a bonding tool such as a wedge tool or a capillary tool, heat and/or ultrasonics is applied to bond the wire to the pad area. Accordingly, when an aluminum pad area is provided in the upper layer and a copper interconnect line is provided in the lower layer, stress exerted by this press may break through the upper aluminum layer, exposing the copper interconnect line thereunder. Copper is more likely to be oxidized than aluminum. As a result, if the copper interconnect line under the pad area is exposed to cause oxidation thereof, poor connection between the pad area and the wire is likely.